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Udemy Basics and Beyond STA Static Timing Analysis

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Uploader:

freecoursewb

Source:

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Type:

Tutorials

Language:

English

Category:

Other

Size:

2.5 GB

Added:

Oct. 23, 2025, 5:53 p.m.

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Files:

Get Bonus Downloads Here.url 180 bytes
1 - Introduction - Why Timing Rules Silicon.en_US.vtt 2.8 KB
1 - Introduction - Why Timing Rules Silicon.mp4 12.6 MB
2 - Design Flow & Where STA Fits (ASICFPGA).en_US.vtt 12.8 KB
2 - Design Flow & Where STA Fits (ASICFPGA).mp4 54.8 MB
3 - What is STA (vs. DTA).en_US.vtt 11.7 KB
3 - What is STA (vs. DTA).mp4 54.0 MB
1 - CMOS Logic & Standard Cells in a Timing Context.en_US.vtt 21.8 KB
1 - CMOS Logic & Standard Cells in a Timing Context.mp4 72.4 MB
2 - Clock Period, Clock Latency, Duty Cycle and Clock Types.en_US.vtt 21.6 KB
2 - Clock Period, Clock Latency, Duty Cycle and Clock Types.mp4 77.5 MB
3 - Propagation Delay, Slew, Skew - Effects & Trade-offs.mp4 46.1 MB
4 - Arrival Time (AT), Required Time (RT), and Slack Basics.mp4 40.6 MB
5 - Introduction of Setup and Hold Times.mp4 115.1 MB
6 - Timing Arcs & Unateness; Path Delay; MinMax Paths.mp4 58.9 MB
7 - Clock Domains & Operating Conditions (PVT), Jitter, Uncertainty.mp4 96.2 MB
1 - End-to-End Path Delay and Path Types.mp4 32.5 MB
2 - Setup Slack Calculation.mp4 73.5 MB
3 - Hold Slack Calculation.mp4 47.4 MB
4 - Setup and Hold Worked Examples (paths in2reg, reg2reg, reg2out) and Fixes.mp4 136.1 MB
1 - Time Borrowing in Latch-Based Designs.mp4 25.9 MB
2 - Multicycle, Half-Cycle Paths & False Paths.mp4 61.9 MB
3 - Critical Path & Metastability - Mean Time Between Failures (MTBF).mp4 44.6 MB
4 - Minimum Pulse Width Checks - Clock Quality in STA.mp4 73.7 MB
5 - Recovery & Removal Checks - Asynchronous Resets in STA.mp4 45.6 MB
6 - Clock Gating and Integrated Clock Gating (ICG) - Checks in STA.mp4 62.1 MB
1 - Inputs and Outputs of STA.mp4 256.4 MB
2 - Non-Linear Delay, CCS and ECSM models.mp4 82.5 MB
3 - Power in Libraries Active, Internal, Leakage.mp4 61.4 MB
1 - Interconnect Delay Models & Pre Layout and Post Layout Parasitics in STA.mp4 83.1 MB
2 - Extracted Parasitics & SPEF (what’s in it, how tools use it).mp4 110.5 MB
3 - Signal Integrity in STA Crosstalk Glitches.mp4 42.0 MB
1 - OCV, AOCV, POCV, SOCV, LVF and Derates in Timing Analysis.mp4 164.5 MB
2 - CPPR (Common Path Pessimism Removal) and Its Impact.mp4 55.9 MB
3 - Useful Skew Clock Push Clock Pull & Closure Tricks.mp4 39.8 MB
4 - Graph Based Analysis (GBA) and Path Based Analysis (PBA) in STA Engine.mp4 88.0 MB
1 - Building the STA Environment SDC Clocks, IO Constraints, Virtual Clocks.mp4 75.8 MB
2 - WNS & TNS; Reading the Timing Reports Across Tools (PrimeTime, Tempus, etc).mp4 189.6 MB
1 - STA Recap, Common Pitfalls & Industry Relevance.mp4 38.9 MB
Bonus Resources.txt 70 bytes

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