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Udemy Mastering Xilinx DSP IP Cores FIR CIC DDS FFT

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Source: 1 Logo 1337x
Downloads: 3062
Type: Tutorials
Language: English
Category: Other
Size: 1.9 GB
Added: April 3, 2025, 9:40 p.m.
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Files:
  1. Get Bonus Downloads Here.url 180 bytes
  2. 1 -Introduction.mp4 41.9 MB
  3. 2 -Requirements and Workflow Automation.mp4 115.4 MB
  4. README.md 2.1 KB
  5. clean.py 1.8 KB
  6. gui_launcher.py 2.0 KB
  7. run_sim.py 2.3 KB
  8. run_vitis.py 2.7 KB
  9. run_vivado.py 2.5 KB
  10. dds_axi_wrapper.v 2.2 KB
  11. tb_util.vh 7.3 KB
  12. create_vitis.py 1.7 KB
  13. dsp_sim.tcl 13.3 KB
  14. cic_main.c 6.7 KB
  15. cic_compiler_tb.v 3.9 KB
  16. cic_compiler_tb_behav.wcfg 4.0 KB
  17. cic_hw.tcl 1.8 KB
  18. cic_sys.tcl 45.9 KB
  19. dds_main.c 7.2 KB
  20. dds_compiler_tb.v 5.6 KB
  21. dds_compiler_tb_behav.wcfg 20.6 KB
  22. dds_hw.tcl 2.0 KB
  23. dds_sys.tcl 45.7 KB
  24. BPF.coe 237 bytes
  25. LPF_dec.coe 237 bytes
  26. LPF_int.coe 237 bytes
  27. hilbert_0.coe 757 bytes
  28. fir_main.c 8.8 KB
  29. fir_compiler_tb.v 7.8 KB
  30. fir_compiler_tb_behav.wcfg 11.9 KB
  31. fir_hw.tcl 1.7 KB
  32. fir_sys.tcl 47.2 KB
  33. xfft_tb.v 5.7 KB
  34. xfft_tb_behav.wcfg 28.7 KB
  35. xfft_hw.tcl 1.7 KB
  36. xfft_sys.tcl 41.1 KB
  37. xfft_main.c 9.3 KB
  38. cic_compiler.py 3.5 KB
  39. dds_compiler.py 4.9 KB
  40. fir_compiler.py 4.1 KB
  41. xfft.py 5.7 KB
  42. 1 -Vivado Simulation FIR compiler v7.2.mp4 311.7 MB
  43. 2 -Vivado Simulation CIC compiler v4.0.mp4 138.4 MB
  44. 3 -Vivado Simulation DDS compiler v6.0.mp4 122.5 MB
  45. 4 -Vivado Simulation Fast Fourier Transform v9.1.mp4 114.8 MB
  46. 1 -Zynq 7000 SoC development C application to interface with FIR compiler IP cores.mp4 341.5 MB
  47. 2 -Zynq 7000 SoC development C application to interface with CIC compiler IP cores.mp4 298.6 MB
  48. 3 -Zynq 7000 SoC development C application to interface with DDS compiler IP cores.mp4 224.3 MB
  49. 4 -Zynq 7000 SoC development C application to interface with FFT IP core.mp4 255.8 MB
  50. Bonus Resources.txt 70 bytes

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